Digital Image Compression Using Approximate Addition

This paper analyzes the usefulness of approximate addition for digital image compression. Discrete Cosine Transform (DCT) is an important operation in We used accurate and individually while calculating DCT to perform Accurate was performed using adder different adders individually. The were implemented application specific integrated circuit (ASIC)-type design environment a 32–28 nm complementary metal oxide semiconductor (CMOS) standard cell library field programmable gate array (FPGA)-based Xilinx Artix-7 device. Error analysis calculate error parameters various by applying one million random input vectors. It observed that help better reduce file size compressed images than adder. Simultaneously, enable reductions compared For ASIC-type implementation cells, optimum achieved 27.1% reduction delay, 46.4% area, 50.3% power high-speed carry look-ahead With respect FPGA-based implementation, 8% delay 19.7% requiring 47.6% fewer look-up tables (LUTs) 42.2% flip-flops native FPGA